HANBit
HMNR1288D(V)
Reading the Clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition.
The TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the
registers can be halted without disturbing the clock itself. Updating is halted when a ’1’ is written to the READ Bit, D6 in the
Control Register (1FFF8h). As long as a ’1’ remains in that position, updating is halted. After a halt is issued, the registers
reflect the count; that is, the day, date, and time that were current at the moment the halt command was is-sued. All of the
TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs
approximately 1 second after the READ Bit is reset to a ’0.’
Setting the Clock
Bit D7 of the Control Register (1FFF8h) is the WRITE Bit. Setting the WRITE Bit to a ’1,’ like the READ Bit, halts updates
to the TIMEKEEPER reg-isters. The user can then load them with the correct day, date, and time data in 24-hour BCD
format. Resetting the WRITE Bit to ’0’ then transfers the values of all time registers (1FFFh-1FFF9h, 1FFF1h) to the actual
TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the next clock update will
occur approximately one second later.
Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset to ’0.’
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the
oscillator can be turned off to minimize current drain on the battery. The STOP Bit is located at Bit D7 within the Seconds
Register (1FFF9h). Setting it to a ’1’ stops the oscillator. When reset to a ’0,’ the HMNR1288D(V) oscillator starts within
one second.
Note : It is not necessary to set the WRITE Bit when setting or resetting the STOP Bit (ST).
Calibrating the Clock
The HMNR1288D(V) is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are
factory calibrated at 25°C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about ± 1.53 minutes per month .
When the Calibration circuit is properly employed, accuracy improves to better than +1/– 2 ppm at 25°C. The oscillation
rate of crystals changes with temperature. The HMNR1288D(V) design employs periodic counter correction. The
calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage. The number of
times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value
loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts
slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register 1FFF8h. These
bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; ’1’ indicates positive
calibration, ’0’ indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle
may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles.
If a binary ’1’ is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is
loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting
256 oscillator cycles for every 125, 829, 120 actual oscillator cycles, that is +4.068 or – 2.034 ppm of adjustment per
calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31
increments in the Calibration byte would represent +10.7 or – 5.35 seconds per month which corresponds to a total range
of +5.5 or – 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given
HMNR1288D(V) may require. The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable
enclosure.
The designer could provide a simple utility that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will
toggle at 512Hz, when the Stop Bit (ST, D7 of 1FFF9h) is ’0,’ the Frequency Test Bit (FT, D6 of 1FFFCh) is ’1,’ the Alarm
Flag Enable Bit (AFE, D7 of 1FFF6h) is ’0,’ and the Watchdog Steering Bit (WDS, D7 of 1FFF7h) is ’1’ or the Watchdog
Register (1FFF7h = 0) is reset.
Note: A 4 second settling time must be allowed before reading the 512Hz output. Any deviation from 512Hz indicates the
degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124Hz would
indicate a +20 ppm oscillator frequency error, requiring a – 10 (WR001010) to be loaded into the Calibration Byte for
correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The
IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10kΩ resistor is
recommended in order to control the rise time. The FT Bit is cleared on power up.
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Rev. 1.0 (April, 2002)
13
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