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GS84032AT-100 参数 Datasheet PDF下载

GS84032AT-100图片预览
型号: GS84032AT-100
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×18 , 128K ×32 , 128K ×36的4Mb同步突发静态存储器 [256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs]
分类和应用: 存储内存集成电路静态存储器时钟
文件页数/大小: 31 页 / 884 K
品牌: GSI [ GSI TECHNOLOGY ]
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Preliminary  
GS84018/32/36AT/B-180/166/150/100  
BGA Pin Description  
Pin Location  
Symbol  
Type  
Description  
N4, P4  
A0, A1  
I
Address field LSBs and Address Counter Preset Inputs  
A2, A3, A5, A6, B3, B5, C2, C3, C5,  
C6, R2, R6, T3, T5  
An  
I
Address Inputs  
T4  
An  
NC  
An  
Address Input (x32/36 Versions)  
No Connect (x32/36 Versions)  
Address Input (x18 Version)  
T2, T6  
T2, T6  
-
I
K7, K6, L7, L6, M6, N7, N6, P7  
H7, H6, G7, G6, F6, E7, E6, D7  
H1, H2, G1, G2, F2, E1, E2, D1  
K1, K2, L1, L2, M2, N1, N2, P1  
DQA1-DQA8  
DQB1-DQB8  
DQC1-DQC8  
DQD1-DQD8  
I/O  
Data Input and Output pins (x32/36 Versions)  
Data Input and Output pins (x36 Version)  
DQA9, DQB9,  
DQC9, DQD9  
P6, D6, D2, P2  
I/O  
P6, D6, D2, P2  
L5, G5, G3, L3  
NC  
-
I
No Connect (x32 Version)  
BA, BB, BC, BD  
Byte Write Enable for DQA, DQB, DQC, DQD I/O’s; active low ( x36 Version)  
P7, N6, L6, K7, H6, G7, F6, E7, D6  
D1, E2, G2, H1, K2, L1, M2, N1, P2  
DQA1-DQA9  
DQB1-DQB9  
I/O  
Data Input and Output pins (x18 Version)  
Byte Write Enable for DQA, DQB I/O’s; active low ( x18 Version)  
No Connect  
L5, G3  
BA, BB  
I
B1, C1, R1, T1, U2, J3, U3, D4, L4,  
U4, J5, U5, U6, B7, C7, R7  
NC  
-
P6, N7, M6, L7, K6, H7, G6, E6, D7,  
D2, B1, E1, F2, G1, H2, K1, L2, N2,  
P1, G5, L3, T4  
NC  
-
No Connect (x18 Version)  
K4  
CK  
BW  
I
I
I
I
I
I
I
I
I
I
I
I
Clock Input Signal; active high  
Byte Write—Writes all enabled bytes; active low  
Global Write Enable—Writes all bytes; active low  
Chip Enable; active low  
M4  
H4  
GW  
E4, B6  
E1, E3  
E2  
B2  
Chip Enable; active high  
F4  
G
Output Enable; active low  
G4  
ADV  
ADSP, ADSC  
ZZ  
Burst address counter advance enable; active low  
Address Strobe (Processor, Cache Controller); active low  
Sleep Mode control; active high  
A4, B4  
T7  
R5  
R3  
FT  
Flow Through or Pipeline mode; active low  
Linear Burst Order mode; active low  
Core power supply  
LBO  
VDD  
J2, C4, J4, R4, J6  
D3, E3, F3, H3, K3, M3, N3, P3, D5,  
E5, F5, H5, K5, M5, N5, P5  
VSS  
I
I
I/O and Core Ground  
A1, F1, J1, M1, U1, A7, F7, J7, M7,  
U7  
VDDQ  
Output driver power supply  
Rev: 1.12 7/2002  
9/31  
© 1999, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com