Preliminary
GS84018/32/36AT/B-180/166/150/100
TQFP Pin Description
Pin Location
Symbol Type
Description
37, 36
A0, A1
A2–A16
A17
I
I
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,
47, 48, 49, 50
Address Inputs
80
Address Inputs (x18 versions)
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
I/O
I/O
Data Input and Output pins. (x32, x36 Version)
18, 19, 22, 23, 24, 25, 28, 29
DQA9, DQB9,
DQC9, DQD9
51, 80, 1, 30
Data Input and Output pins (x36 Version)
No Connect (x32 Version)
51, 80, 1, 30
NC
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1–DQA9
DQB1–DQB9
I/O
-
Data Input and Output pins (x18 Version)
51, 52, 53, 56, 57
75, 78, 79
NC
No Connect (x18 Version)
1, 2, 3, 6, 7
25, 28, 29, 30
87
BW
I
I
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/’s; active low
93, 94
BA, BB
Byte Write Enable for DQC, DQD Data I/Os; active low
(x32, x36 Version)
95, 96
BC, BD
I
95, 96
NC
-
I
I
I
I
I
I
I
I
I
I
I
No Connect (x18 Version)
Clock Input Signal; active high
89
CK
88
GW
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
98, 92
E1, E3
97
E2
Chip Enable; active high
86
G
ADV
Output Enable; active low
83
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
84, 85
ADSP, ADSC
ZZ
64
14
31
FT
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
LBO
V
15, 41, 65, 91
DD
V
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
16, 38, 39, 42, 43, 66
I
I
I/O and Core Ground
Output driver power supply
No Connect
SS
V
DDQ
NC
-
Rev: 1.12 7/2002
5/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GSI [ GSI TECHNOLOGY ]
