Preliminary
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1
tKL
tKH
Read C
tKC
Cont
Read D
Write E
Read F
Write G
CK
CKE
E*
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
ADV
W
Bn
A0–An
DQ
A
B
C
D
E
F
G
tH
tKQ
tLZ
tKQX
tKQ
tLZ
tS
D(A)
tHZ
tKQX
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
Rev: 1.00 9/2004
25/37
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
