欢迎访问ic37.com |
会员登录 免费注册
发布采购

GS4576C18GL-33T 参数 Datasheet PDF下载

GS4576C18GL-33T图片预览
型号: GS4576C18GL-33T
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用:
文件页数/大小: 62 页 / 2381 K
品牌: GSI [ GSI TECHNOLOGY ]
 浏览型号GS4576C18GL-33T的Datasheet PDF文件第49页浏览型号GS4576C18GL-33T的Datasheet PDF文件第50页浏览型号GS4576C18GL-33T的Datasheet PDF文件第51页浏览型号GS4576C18GL-33T的Datasheet PDF文件第52页浏览型号GS4576C18GL-33T的Datasheet PDF文件第54页浏览型号GS4576C18GL-33T的Datasheet PDF文件第55页浏览型号GS4576C18GL-33T的Datasheet PDF文件第56页浏览型号GS4576C18GL-33T的Datasheet PDF文件第57页  
GS4576C09/18/36L  
TAP Controller Block Diagram  
0
Bypass Regsiter  
7
6
5
4
3
2
1
0
0
Instruction Regsiter  
Selection  
circuitry  
Selection  
circuitry  
TDO  
TDI  
31 30 29  
.
.
.
2
1
Identification Regsiter  
x1  
.
.
.
.
.
2
1
0
Boundary Scan Regsiter  
TCK  
TMS  
TAP Controller  
Note:  
x= 112 for all configurations  
Performing a TAP RESET  
A reset is performed by forcing TMS High (V  
) for five rising edges of TCK. This RESET does not affect the operation of the  
DDQ  
LLDRAM II and may be performed while the LLDRAM II is operating.  
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.  
TAP Registers  
Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the LLDRAM II test  
circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the  
rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.  
Instruction Register  
Eight-bit instructions can be serially loaded into the instruction register. This register is loaded during the Update-IR state of the  
TAP controller. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as described in the previous section.  
When the TAP controller is in the Capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for fault isolation  
of the board-level serial test data path.  
Bypass Register  
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is  
a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the LLDRAM II with  
minimal delay. The bypass register is set Low (V ) when the BYPASS instruction is executed.  
SS  
Rev: 1.04 11/2013  
53/62  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
 复制成功!