Preliminary
GS4288C09/18/36L
Burst Length
Read and Write data transfers occur in bursts of 2, 4, or 8 beats. Burst Length is programmed by the user via Mode Register Bit 3
(M3) and Bit 4 (M4). The Read Burst Length diagrams illustrate the different burst lengths with respect to a Read Command.
Changes in the burst length affect the width of the address bus.
Note: Changing the burst length configuration may scramble previously written data. A burst length change must be assumed to
invalidate all stored data.
Read Burst Lengths
Example BL=2
CK
CK
Command
READ
READ
READ
RL = 5
RL = 5
RL = 5
QKx
QKx
QVLD
DQ
Q0
Q1
Example BL=4
CK1
CK1
Command1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
QKx1
QKx1
QVLD1
DQ1
Q0
Q1
Q2
Q3
Example BL=8
CK2
CK2
Command2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
QKx2
QKx2
QVLD2
DQ2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Address Widths at Different Burst Lengths
Configuration
x18
Burst Length
x9
x36
2
4
8
A0–A20
A0–A19
A0–A18
A0–A19
A0–A18
A0–A17
A0–A18
A0–A17
A0–A16
Rev: 1.02 3/2013
19/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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