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G2996P1UF 参数 Datasheet PDF下载

G2996P1UF图片预览
型号: G2996P1UF
PDF下载: 下载PDF文件 查看货源
内容描述: DDR I / II终端稳压器 [DDR I/II Termination Regulator]
分类和应用: 稳压器双倍数据速率
文件页数/大小: 13 页 / 282 K
品牌: GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
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Global Mixed-mode Technology Inc.
Pin Description
NUMBER
1
2
3
4
5
6
7
8
G2996
NAME
GND
SD
FUNCTION
Ground
Active low shutdown control pin
Feedback pin for regulating V
TT
Buffered output that is a reference output of VDDQ/2
Power Input for internal reference
Analog input pin
Power input pin
Output voltage for connection to termination resistors, equal to VDDQ/2
VSENSE
VREF
VDDQ
AVIN
PVIN
VTT
Block Diagram
SD
V
DDQ
AV
IN
PV
IN
50k
V
REF
+
+
50k
-
-
V
TT
V
SENSE
GND
Description
The G2996 is a linear bus termination regulator de-
signed to meet the JEDEC SSTL-2 and SSTL-3 (Se-
ries Stub Termination Logic) specifications for termina-
tion of DDR-SDRAM. The output, V
TT
, is capable of
sinking and sourcing current while regulating the out-
put voltage equal to VDDQ/2. The G2996 is designed
to maintain the excellent load regulation and with fast
response time to minimum the transition preventing
shoot-through. The G2996 also incorporates two dis-
tinct power rails that separates the analog circuitry
(AVIN) from the power output stage (PVIN). This
power rails split can be utilized to reduce the internal
power dissipation. And this also permits G2996 to pro-
vide a termination solution for the next generation of
DDR-SDRAM (DDR II).
Series Stub Termination Logic (SSTL) was created to
improve signal integrity of the data transmission
across the memory bus. This termination scheme is
essential to prevent data error from signal reflections
while transmitting at high frequencies encountered
with DDR-SDRAM. The most common form of termi-
nation is Class II single parallel termination. This in-
volves one RS series resistor from the chipset to the
memory and one RT termination resistor, both 25
Ω
typically. The resistors can be changed to scale the
current requirements from the G2996. This implemen-
tation can be seen below in Figure 1.
Ver: 2.3
May 16, 2006
V
DD
V
TT
R
T
R
S
CHIPSET
MENORY
V
REF
Figure 1. SSTL-Termination Scheme
AVIN, PVIN
AVIN and PVIN are two independent input supply pins
for the G2996. AVIN is used to supply all the internal
analog circuits. PVIN is only used to supply the output
stage to create the regulated V
TT
. To keep the regula-
tion successfully, AVIN should be equal to or larger
than PVIN. Using a higher PVIN voltage will produce a
larger sourcing capability from V
TT.
But the internal
power loss will also increase and then the heat in-
creases. If the junction temperature exceeds the
thermal shutdown threshold than the G2996 will enter
the shutdown state that is the same as manual shut-
down, where V
TT
is tri-state and V
REF
remains active.
For SSTL-2 applications, the AVIN and PVIN can be
short together at 2.5V to minimize the PCB complexity
and to reduce the bypassing capacitors for the two
supply pins separately.
TEL: 886-3-5788833
http://www.gmt.com.tw
8