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G2996P1UF 参数 Datasheet PDF下载

G2996P1UF图片预览
型号: G2996P1UF
PDF下载: 下载PDF文件 查看货源
内容描述: DDR I / II终端稳压器 [DDR I/II Termination Regulator]
分类和应用: 稳压器双倍数据速率
文件页数/大小: 13 页 / 282 K
品牌: GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
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Global Mixed-mode Technology Inc.  
G2996  
Typical Application Circuits  
There are several application circuits shown in Figure  
2 through 8 to illustrate some of the possible configu-  
rations of the G2996. Figure 2~4 are the SSTL-2 ap-  
plications. For the majority of applications that imple-  
ment the SSTL-2 termination scheme, it is recom-  
mended to connect all the input rails to 2.5V rail, as  
seen in Figure 2. This provides an optimal trade-off  
between power dissipation and component count.  
SD  
SD  
VREF  
VREF=1.25V  
CREF  
+
+
VDDQ  
AVIN  
PVIN  
VDDQ=2.5V  
DD=2.5V  
VSENSE  
VTT  
V
VTT=1.25V  
COUT  
+
GND  
CIN  
Figure 2. Recommended SSTL-2 Implementation  
In Figure 3, the power rails are split. The power rail of  
the output stage (PVIN) can be as low as 1.8V, the  
power rail of the analog circuit (AVIN) is operated  
above 2V. The lower output stage power rail can lower  
the internal power dissipation when sourcing from the  
device and improve the efficiency, but the disadvan-  
tage is the maximum continuous current sourcing from  
VTT is reduced. This configuration is applied when the  
power dissipation and efficiency are concerned.  
SD  
VREF  
VREF=1.25V  
SD  
+
+
CREF  
VDDQ  
VDDQ=2.5V  
VSENSE  
VTT  
AVIN=1.8V or 5.5V  
PVIN=1.8V  
AVIN  
PVIN  
VTT=1.25V  
COUT  
+
GND  
CIN  
Figure 3. Lower Power Dissipation SSTL-2 Implementation  
In Figure 4, the power rail of the output stage (PVIN) is  
should be more careful to prevent the junction tem-  
perature from exceeding the maximum rating. Be-  
cause of this risk, it is not recommended to supply the  
output stage power rail (PVIN) with a voltage higher  
than a nominal 3.3V rail.  
connected to 3.3V to increase the maximum continu-  
ous current sourcing from VTT. AVIN should be always  
equal to or larger than PVIN. This configuration can  
increase the source capability of this device, but the  
power dissipation increases at the same time. It  
SD  
VREF  
VREF=1.25V  
CREF  
SD  
+
+
VDDQ  
VDDQ=2.5V  
VSENSE  
VTT  
AVIN=3.3V or 5V  
PVIN=3.3V  
AVIN  
PVIN  
VTT=1.25V  
COUT  
+
GND  
CIN  
Figure 4. SSTL-2 Implementation with higher voltage rails  
Ver: 2.3  
May 16, 2006  
TEL: 886-3-5788833  
http://www.gmt.com.tw  
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