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GD25Q80CSIG 参数 Datasheet PDF下载

GD25Q80CSIG图片预览
型号: GD25Q80CSIG
PDF下载: 下载PDF文件 查看货源
内容描述: [3.3V Uniform Sector Dual and Quad Serial Flash]
分类和应用:
文件页数/大小: 56 页 / 1271 K
品牌: GILWAY [ GILWAY TECHNICAL LAMP ]
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3.3V Uniform Sector  
Dual and Quad Serial Flash  
GD25Q80C  
7. COMMANDS DESCRIPTION  
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the  
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most  
significant bit first on SI, each bit being latched on the rising edges of SCLK.  
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might  
be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command  
sequence has been shifted in. For the commands of Read, Fast Read, Read Status Register or Release from Deep Power-  
Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high  
after any bit of the data-out sequence is being shifted out.  
For the commands of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,  
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command  
is rejected, and is not executed. That means CS# must be driven high when the number of clock pulses after CS# being  
driven low is an exact multiple of eight. For Page Program, if CS# is driven high at any time the input byte is not a full byte,  
nothing will happen and WEL will not be reset.  
Table2. Commands (Standard/Dual/Quad SPI)  
Command Name  
Byte 1  
06H  
Byte 2  
Byte 3  
Byte 4  
Byte 5  
Byte 6  
n-Bytes  
Write Enable  
Write Disable  
Volatile SR  
04H  
50H  
Write Enable  
Read Status Register  
05H  
(S7-S0)  
(S15-S8)  
(S7-S0)  
A23-A16  
A23-A16  
A23-A16  
(continuous)  
(continuous)  
Read Status Register-1 35H  
Write Status Register  
Read Data  
Fast Read  
01H  
03H  
0BH  
3BH  
(S15-S8)  
A15-A8  
A15-A8  
A15-A8  
A7-A0  
A7-A0  
A7-A0  
(D7-D0)  
dummy  
dummy  
(Next byte)  
(D7-D0)  
(D7-D0)(1)  
(continuous)  
(continuous)  
(continuous)  
Dual Output  
Fast Read  
Dual I/O  
Fast Read  
BBH  
6BH  
EBH  
E7H  
A23-A8(2)  
A23-A16  
A7-A0  
(D7-D0)(1)  
A7-A0  
(continuous)  
(continuous)  
(continuous)  
(continuous)  
M7-M0(2)  
Quad Output  
Fast Read  
A15-A8  
dummy  
(D7-D0)(3)  
Quad I/O  
Fast Read  
A23-A0  
M7-M0(4)  
A23-A0  
M7-M0(4)  
dummy(5)  
dummy(6)  
(D7-D0)(3)  
(D7-D0)(3)  
Quad I/O Word  
Fast Read(7)  
Continuous Read Mode FFH  
Reset  
Page Program  
Quad Page Program  
Sector Erase  
02 H  
32H  
20H  
52H  
D8H  
C7/60  
H
A23-A16  
A23-A16  
A23-A16  
A23-A16  
A23-A16  
A15-A8  
A15-A8  
A15-A8  
A15-A8  
A15-A8  
A7-A0  
A7-A0  
A7-A0  
A7-A0  
A7-A0  
(D7-D0)  
(D7-D0)(3)  
Next byte  
Block Erase(32K)  
Block Erase(64K)  
Chip Erase  
Enable Reset  
Reset  
66H  
99H  
77H  
75H  
Set Burst with Wrap  
Program/Erase  
Suspend  
W6-W4  
Program/Erase Resume 7AH  
13  
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