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GD25Q80CSIG 参数 Datasheet PDF下载

GD25Q80CSIG图片预览
型号: GD25Q80CSIG
PDF下载: 下载PDF文件 查看货源
内容描述: [3.3V Uniform Sector Dual and Quad Serial Flash]
分类和应用:
文件页数/大小: 56 页 / 1271 K
品牌: GILWAY [ GILWAY TECHNICAL LAMP ]
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3.3V Uniform Sector  
Dual and Quad Serial Flash  
GD25Q80C  
6. STATUS REGISTER  
S15  
S14  
S13  
S12  
S11  
S10  
LB  
S9  
S8  
SUS  
CMP  
HPF  
Reserved  
Reserved  
QE  
SRP1  
S7  
S6  
S5  
S4  
S3  
S2  
S1  
S0  
SRP0  
BP4  
BP3  
BP2  
BP1  
BP0  
WEL  
WIP  
The status and control bits of the Status Register are as follows:  
WIP bit.  
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.  
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,  
means the device is not in program/erase/write status register progress.  
WEL bit.  
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal  
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or  
Erase command is accepted.  
BP4, BP3, BP2, BP1, BP0 bits.  
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software  
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.  
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in  
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block  
Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.  
The Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0.  
SRP1, SRP0 bits.  
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP  
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time  
programmable protection.  
SRP1 SRP0 #WP  
Status Register  
Description  
The Status Register can be written to after a Write Enable  
command, WEL=1.(Default)  
0
0
X
Software Protected  
WP#=0, the Status Register locked and can not be written  
to.  
0
1
0
Hardware Protected  
WP#=1, the Status Register is unlocked and can be written  
to after a Write Enable command, WEL=1.  
0
1
1
0
1
1
X
X
Hardware Unprotected  
Power Supply Lock-Down(1) Status Register is protected and can not be written to again  
(2)  
until the next Power-Down, Power-Up cycle.  
Status Register is permanently protected and can not be  
written to.  
1
One Time Program(2)  
NOTE:  
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.  
2. This feature is available on special order. Please contact GigaDevice for details.  
QE bit.  
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When  
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