3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q80C
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status
Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS#
goes low sending the Write Enable command CS# goes high.
Figure 2. Write Enable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
06H
High-Z
SO
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-
up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,
Erase/Program Security Registers and Reset commands.
Figure 3. Write Disable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
04H
High-Z
SO
7.3. Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. The
command code “35H”, the SO will output Status Register bits S15~S8.
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GILWAY [ GILWAY TECHNICAL LAMP ]
