GS9090 Data Sheet
Table 2-3: AC Electrical Characteristics (Continued)
VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units
Notes
Serial Digital Input
Serial Input Data Rate
DRSDI
–
–
–
270
–
Mb/s
–
Serial Input Jitter Tolerance
IJT
–
0.4
–
UI
2
3
Serial Digital Input Signal Swing
ΔVDDI
Differential with
internal 100Ω input
termination
400
800
1700
mVp-p
Parallel Output
Parallel Output Clock Frequency
Parallel Output Clock Duty Cycle
fPCLK
DCPCLK
–
–
–
–
27
–
–
MHz
%
–
–
4
40
60
Variation of Parallel Output Clock
(from 27MHz)
Device Unlocked
-7.5
–
+7.5
%
TA = -20°C to +85°C
IO_VDD = 1.8V
With 15pF load
Output Data Hold Time
Output Delay Time
tOH
tOD
3.0
–
–
–
–
ns
ns
5
5
With 15pF load
10.0
GSPI
GSPI Input Clock Frequency
GSPI Clock Duty Cycle
GSPI Setup Time
GSPI Hold Time
NOTES:
fGSPI
DCGSPI
tGS
–
–
–
–
–
40
1.5
–
–
–
–
–
54.0
60
MHz
%
–
–
–
–
–
ns
tGH
1.5
ns
1. No signal to signal present, or a switch from another data rate to 270Mb/s.
2. Power supply noise 50mVpp at 15kHz, 100kHz, 1MHz sinusoidal modulation.
3. See Figure 2-1.
4. When the serial input to the GS9090 is removed, the PCLK output signal will continue to operate at 27MHz and the internal VCO will
remain at this frequency within +/- 7.5% over the range -20oC to +85oC.
5. Timing includes the following outputs: DOUT[9:0], STAT[3:0]. When the FIFO is enabled, the outputs are measured with respect to
RD_CLK.
28201 - 1 July 2005
14 of 70
GENNUM [ GENNUM CORPORATION ]
