5.3 Host Interface Read/Write Timing
flow through the chip unprocessed during resetting. An
internal power-on-reset cell is also present in the device so
that device initialization occurs on power-up. Figure 10a
illustrates the reset circuitry. The internal power-on reset
circuit of the GS9021 is sensitive to the rise time of the
power supply, hence an external power on reset chip or
Figure 9 illustrates valid times for reading/writing information
from the HOSTIF tables. Figure 9 represents two fields of
video data entering and exiting the GS9021. The relative
position of the EDH packet in the data stream is also shown.
(Note that the EDH packet entering the device at t0, EDH
F0, represents the EDH information from the previous field,
FIELD 0).
board level reset line is strongly recommended.
When
using this technique, the user must ensure that a minimum
pulse width of 100ns is present on the reset line.
It is safe to read or write EDH information at least two lines
after an EDH packet exits the chip but before the
subsequent EDH packet enters the chip. Reading during
the time interval shown will show values from EDH F0.
Writing during the time interval shown will affect EDH F1.
In applications where a board-level reset is not available, a
circuit similar to figure 10b can be used to ensure correct
reset on power-up. The RESET pin will typically take 1.4ms
to reach 2.5V on power up, but can take longer for power
supplies with slower rise times. A bleed resistor such as
the one shown (20k) will assist the capacitor to discharge
once power is removed. The user should allow the
capacitor to discharge to at least 0.5V before power is
reapplied, to permit a full internal reset. The time taken by
the RESET pin to reach 0.5V on power down, is dependent
upon the fall time of the power supply.
Note that the above read/write timing should also be
observed when reading/writing flag information via the
FLAG PORT.
6.0 RESET
PIN
LOGIC OPR
HOST BIT
RESET
Setting the RESET input pin LOW re-initializes the internal
control circuitry including returning all HOST interface
programming values to their original default values. The
data pipe is not affected by the reset, so data continues to
t
H
SYNCHRONOUS
INPUTS
t
S
PCLKIN
Fig. 1 Input Setup & Hold Times (Synchronous Inputs)
SYNCHRONOUS
OUTPUTS
DATA
VALID
t
OS
t
OH
t
PCLKIN
OD
Fig. 2 Output Delay & Hold Times (Synchronous Outputs)
17
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