3.11 Bypass EDH Processing
Similarly, if TRS_BLANK is enabled and TRS_INSERT is not,
then there may be 0 TRS per line during a switch. In most
applications, these features should be either both enabled
or both disabled to maintain only two TRSs per line. TRS
blanking will function incorrectly if the flywheel is disabled.
Thus if the flywheel is disabled the TRS_BLANK function
should be disabled as well.
PIN
LOGIC OPR
OR
HOST BIT
BYPASS_EDH
BYPASS_EDH
EDH processing can be bypassed by asserting the
BYPASS_EDH pin or HOSTIF write table bit HIGH. When
bypassed, EDH packets pass through the chip unaltered.
Overwriting information in the EDH packet via the HOSTIF
write table or the FLAG PORT has no effect. Data
processing in the chip (as described below) can still occur
even if BYPASS_EDH is asserted. In this case, valid
incoming error flags can be read via the I²C or parallel port
interface. However, reading outgoing error flags via the host
port or the flag port returns values of 0.
4.2 ITU-R-601 Clipping
PIN
LOGIC OPR
HOST BIT
601_CLIP
This feature operates on the active picture portion (as
defined in RP165) of the data stream only. When the
601_CLIP bit of the HOSTIF write table is asserted HIGH,
the device remaps all reserved data words in the active
picture to values compliant with ITU-R-601. That is, 000-003
is clipped to 004 and 3FCH -3FFH is clipped to 3FBH.
4. DATA PROCESSING BLOCK
The GS9021 contains advanced data processing features
that can simplify system design requirements. These
include:
4.3 Data Blanking
•
•
•
•
•
TRS Blanking,
ITU-R-601 Clipping
Data Blanking,
PIN
LOGIC OPR
HOST BIT
BLANK_EN
AND
BLANK_EN
TRS Insertion, and
ANC Header updating
Asserting the BLANK_EN pin or the corresponding HOSTIF
write table bit LOW causes the corresponding input data to
be forced to blanking levels. This is a dynamic control
allowing the user to individually select which data words are
to be blanked as shown in Figure 7. TRS and EDH insertion
occurs after data blanking so if all these features are being
used, the output data stream continues to have TRS words
and EDH packets present, even if the BLANK_EN is
constantly held LOW.
It is important to note that these processing functions occur
in the GS9021 in the order listed above.
When implementing applications which use the EDH core
(ie. BYPASS_EDH set LOW), TRS blanking, data blanking,
and TRS insertion will indicate a downstream FF/AP EDH
error when a 3FCH-3FFH input data value is blanked out or
overwritten to a value less than 3FBH. As such, users may
wish to disable data blanking, TRS blanking and TRS
insertion by setting the BLANK_EN pin HIGH, the CLIP_TRS
pin LOW, and leaving the corresponding host interface bits
at their power-on default values.
The outgoing EDH packet will contain the correct CRC
values for the blanked fields since the CRC values are
calculated and inserted just prior to the data exiting the
device.
The blanking values in hexi-decimal notation for each
standard are as follows:
4.1 TRS Blanking
PIN
LOGIC OPR
HOST BIT
NTSC/PAL 4:2:2
NTSC 4ƒsc
200 040 200 040 (CB:Y:CR:Y)
TRS_BLANK
0F0
100
PAL 4ƒsc
When asserted HIGH, TRS_BLANK (HOSTIF write table) will
blank out any incorrectly positioned TRS words with respect
to the flywheel. The blanking values used will be
appropriate for the detected video standard as described
below in the Data Blanking section. When TRS_INSERT is
enabled and TRS_BLANK is not, there may be 4 TRSs per
line in the outgoing data stream during a standard switch.
NTSC/PAL 4:4:4:4
040 040 040 040 (B:G:R:A)
200 040 200 040 (CB:Y:CR:A)
14
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GENNUM [ GENNUM CORPORATION ]
