WRITE CYCLE
READ CYCLE
DATA
P[7:0]
DATA IN
ADDRESS
ADDRESS
DATA
R/W
A/D
CS
t
t
t
t
t
0
1
4
3
2
Fig. 14c HOSTIF Parallel Port READ/WRITE Cycles
FIELD 1
FIELD 0
FIELD 2
SDI/SDI
EDH F0
EDH F1
t
0
E
D
H
F1
E
D
H
F0
DOUT[9:0]
VALID TIME TO READ/WRITE
EDH INFORMATION TO/FROM GS9020
2 LINES
Fig. 15 Host Interface READ/WRITE Timing
~1.4 mS
t
= 25µs
V
MAX
DD
V
DD
5V
INTERNAL
POWER on
2k
RESET CELL
0V
t
RESET
RESET
INTERNAL
RESET
SIGNAL
Manual
Reset
Switch
5V
RESET
PIN
20k
1uF
(Optional)
t
RESET
0V
t
Fig. 16a Reset Circuitry
Fig. 16b Acceptable external reset circuit when a master reset is
not available
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