SDI CLOCK
SYNCHRONOUS
INPUTS
VALID
t
SERIAL DATA
2
PCLKOUT
t
t
SS
1
t
SH
Fig. 1 Serial Data Input Setup & Hold Times
Fig. 2 Input Setup & Hold Times (Synchronous Inputs)
V
, SDI
R
V
, SDI
DD
DD
PULLUP
R
PULLUP
SYNCHRONOUS
OUTPUTS
DATA
VALID
SDI
SDI
t
OS
t
OH
t
PCLKOUT
OD
Fig. 3 Output Delay & Hold Times (Synchronous Outputs)
Fig. 4 Serial Data & Clock Input Circuit
V
V
DD
DD
V
V
DD
DD
GS9025A
GS9020A
V
SDI
, SDI
DD
SDO
SDO
SDO
SDO
SDI
V
, SDI
, SCI
DD
V
DD
SCO
SCO
SCI
SCI
V
, SCI
DD
Fig. 5 Interfacing the GS9020A to the GS9025A
Fig. 6 Serial Data Output Circuit
V
DD
GS9025A
GS9020A
, SDI
GS9028
V
DD
Z
SDO
SDO
SDI
SDI
0
SDO
SDO
SDI
SDI
SDO
Ι
+
SDO
V
, SDI
DD
V
2Z
DIFF OUT
0
V
, SCI
DD
-
SCO
SCO
GS9025
SCI
SCI
V
, SCI
V
= Ι
x 2Z
DD
DIFF OUT
SDO
0
SDOMODE
Fig. 7 Interfacing the GS9020A to the GS9028
23 of 31
19922 - 3
GENNUM [ GENNUM CORPORATION ]
