WRITE CYCLE
READ CYCLE
F_R//W
FL[4:0]
XX
FF
AP
ANC
S
XX
FF
AP
ANC
S
11
11
PCLKOUT
S[1:0]
t
t
t
t
t
5
t
t
7
t
1
2
t
6
3
0
4
8
00
01
11
01
10
10
00
XX
11
Fig. 12a Flag Port READ/WRITE Timing
F_R/W
F_R/W
FL [4:0]
t
FEN
FL [4:0]
t
FDIS
PCLKOUT
PCLKOUT
Fig. 12b Flag Port Disable Time
Fig. 12c Flag Port Enable Time
PCLKOUT
X
F_R/W
FLAGMAP
AP
01
FF
00
ANC
10
ANC
10
AP
01
FF
00
ANC
10
FL[4:0]
S[1:0]
XX
XX
XX
1
XX
2
2
0
0
XX XX
1
t
FEN
Flags held at ANC between EDH packets
Double clocking
Fig. 12d Flag Port Timing in FLAG MAP MODE
GS9020A
or
GS9021A
GS9021A
PROCESSING
WHICH DOES NOT
AFFECT THE
CRC_MODE = 0
CRC_MODE = 1
R/T = 1 (GS9021A)
EDH PACKET
Fig. 13a Example of CRC_MODE Implementation
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