V
V
V
DD
DD
DD
R
EXT
SWC
6k8
OUTPUT
C
EXT
EXTERNAL
COMPONENTS
GND
Fig. 5 Pin 15 SWC
Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28
SWF, HSYNC, SSI, SSD, PCLK, PD0-9
1
1
/
T
/
T
2
2
tCLKL = tCLKH
PARALLEL
DATA
(PDn)
50ꢀ
SERIAL
CLOCK
(SCI)
PARALLEL
CLOCK
(PCLK)
SERIAL
DATA
(SDI)
50ꢀ
tHOLD
tSU
tD
Fig. 7 Waveforms
TEST SET-UP & APPLICATION INFORMATION
If the automatic standard select function is not used, the
Standard Select bits (pins 9 and 10) do not need to be
connected, however the control input (pin 11) should be
grounded.
Figure 8 shows the test set-up for the GS9000D operating
from a VDD supply of +5 volts. The differential pseudo ECL
inputs for DATA and CLOCK (pins 5,6,7 and 8) must be
biased between +3.0 and +4.05 volts. In the application
circuit shown in Figure 11, these inputs can be directly
driven from the outputs of the GS7025 Reclocking Receiver
with their resistor values set as shown.
In other cases, such as true ECL level driver outputs, two
biasing resistors are needed on the DATA and CLOCK
inputs and the signals must be AC coupled.
It is critical that the decoupling capacitors connected to
pins 12,13 and 18 are chip types and are located as close
as possible to the device pins.
The critical high speed inputs, such as Serial Data
(pins 5 and 6) and Serial Clock (pins 7 and 8), are located
along one side of the device package to maintain very short
interconnections when interfacing with the GS7025
Receiver.
6 of 9
GENNUM CORPORATION
18784 - 3
GENNUM [ GENNUM CORPORATION ]
