( M S B )
P D 9
V
S W F
3
V
H S Y N C
P D 8
27
V
S S
S S
4
S S
2
28
26
SDI
SDI
SCI
SCI
SS1
SS0
SSC
PD7
PD6
PD5
PD4
PD3
PD2
PD1
5
6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
7
GS9000D
TOP VIEW
8
9
1 0
1 1
12
13
14
15
16
17
18
V
V
S C E
S W C
P C L K
P D 0
V
D D
D D
D D
( L S B )
Fig. 1 GS9000D Pin Outs, 28 Pin PLCC Package
PIN DESCRIPTIONS
PIN NO.
SYMBOL
TYPE
DESCRIPTION
1
2
3
HSYNC
VSS
Output
Horizontal Sync Output. CMOS (TTL compatible) output that toggles for each TRS detected.
Power Supply. Most negative power supply connection.
SWF
Output
Sync Error Warning Flag. CMOS (TTL compatible) active high output that indicates the
preselected HSYNC Error Rate (HER). The HER is set with an RC time constant on the SWC
input.
4
VSS
Power Supply. Most negative power supply connection.
5, 6
SDI/SDI
Inputs
Inputs
Output
Input
Differential, pseudo-ECL serial data inputs. ECL voltage levels with offset of 3.0V to 4.05V for
operation up to 270MHz. See AC Electrical Characteristics Table for details.
7, 8
9,10
11
SCI/SCI
SS1/SS0
SSC
Differential, pseudo-ECL serial clock inputs. ECL voltage levels with offset of 3.0V to 4.05V for
operation up to 270MHz. See AC Electrical Characteristics Table for details.
Standard Select Outputs. CMOS (TTL compatible) outputs is generated by a 2-bit internal
binary counter which stops cycling when a valid TRS is detected by the GS9000D.
Standards Select Control. Analog input used to set a time constant for the standards select
hunt period. An external RC sets the time constant.
12
13
14
VDD
VDD
Power Supply. Most positive power supply connection.
Power Supply. Most positive power supply connection.
SCE
Input
Sync Correction Enable. Active high CMOS input which enables sync correction by not
resetting the GS9000D’s internal parallel timing on the first sync error. If the next incoming
sync is in error, internal parallel timing will be reset. This is to guard against spurious HSYNC
errors. When SCE is low, a valid sync will always reset the GS9000D’s parallel timing generator
4 of 9
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