PIN DESCRIPTIONS
PIN NO.
15
16
17
18
19-25
26
27
28
SYMBOL
SWC
PCLK
PD0
V
DD
PD1 - PD7
V
SS
PD8
PD9
Output
Output
Outputs
TYPE
Input
Output
Output
DESCRIPTION
Sync Warning Control.
Analog input used to set the HSYNC Error Rate (HER). This is
accomplished by an external RC time constant connected to this pin.
Parallel Clock Output.
CMOS (TTL compatible) clock output where the rising edge of the
clock is located at the centre of the parallel data window within a given tolerance. See Fig. 7.
Parallel Data Output - Bit 0 (LSB).
CMOS (TTL compatible) descrambled parallel data output
from the serial to parallel convertor representing the least significant bit (LSB).
Power Supply.
Most positive power supply connection.
Parallel Data Outputs - Bit 1 to Bit 7.
CMOS (TTL compatible) descrambled parallel data
outputs from the serial to parallel convertor representing data bit 1 through data bit 7.
Power Supply.
Most negative power supply connection.
Parallel Data Output.
CMOS (TTL compatible) descrambled parallel data output from the
serial to parallel convertor representing data bit 8.
Parallel Data Output - Bit 9 (MSB).
CMOS (TTL compatible) descrambled data output from
the serial to parallel convertor representing the most significant bit (MSB).
GS9000D
INPUT/OUTPUT CIRCUITS
V
DD
V
DD
V
DD
R
EXT
SSC
SDI
SCI
EXTERNAL
COMPONENTS
V
DD
BIAS
Fig. 2 Pin 11 SSC
SDI
SCI
V
DD
V
DD
Fig. 4 Pins 5 - 8 SDI - SCI
SCE
Fig. 3 Pin 14 SCE
5 of 9
GENNUM CORPORATION
18784 - 3
GENNUM [ GENNUM CORPORATION ]
