GS4901B/GS4900B Preliminary Data Sheet
3.2.1 Genlock Mode
When the application layer sets the GENLOCK pin LOW and the device has
successfully genlocked the outputs to the input reference, the GS4901B/GS4900B
will enter Genlock mode. In this mode, all clock and timing generator outputs will
be frequency and phase locked to the detected input reference signal. The PCLK
outputs will be locked to the H reference.
When in Genlock mode, the output clock and timing signals are generated using
the applied reference signal. The 27MHz crystal reference is necessary for
operation; however, neither crystal accuracy nor changes in crystal frequency (due
to a shift in operating temperature) will affect the output signals. For example, the
output signals will be generated with the same accuracy whether the 27MHz
reference crystal has an accuracy of 10ppm or 100ppm.
The GS4901B/GS4900B supports cross-locking, allowing the outputs to be
genlocked to an incoming reference that is different from the output video standard
selected (see Section 3.6 on page 46).
NOTE: The user must apply a reference to the input of the device prior to setting
GENLOCK = LOW. If the GENLOCK pin is set LOW and no reference signal is
present, the generated clock and timing outputs of the device may correspond to
the internal default settings of the chip until a reference is applied.
3.2.1.1 Genlock Timing Offset
By default, the phase of the clock and timing out signals is genlocked to the input
reference signal. These output signals may be phase adjusted with respect to the
input reference by programming the host interface (see Section 3.10.3 on
page 66). Offsets are separately programmable in terms of clock phase, horizontal
phase, and vertical phase (i.e. fractions of a pixel, pixels, and lines).
Genlock timing offsets can be used to co-time the output of a piece of equipment
containing the GS4901B/GS4900B with the outputs of other equipment at different
locations. The signal leaving the piece of equipment containing the
GS4901B/GS4900B may pass through processing equipment with significant fixed
delays before arriving at the switcher. These delays may include video line delays
or even field delays. To compensate for these delays, genlock timing offsets allow
the user to back-time the output of the equipment relative to the input reference.
Using the host interface, the following registers may be programmed once the
device is stably locked:
•
Clock_Phase_Offset (1Dh) - with a range of zero to one clock pulse in
increments of between 1/128 and 1/512 of a clock period (depending on the
PCLK frequency). The increments will be between 100ps and 150ps. All clock
and timing output signals will be delayed by the clock phase offset
programmed in this register.
•
H_Offset (1Bh) - the difference between the reference HSYNC signal and the
output H Sync and/or H Blanking signal in clock pulses, with a control range of
zero to +1 line. All timing output signals will be delayed by the horizontal offset
programmed in this register.
37703 - 0 April 2006
35 of 95
GENNUM [ GENNUM CORPORATION ]
