GS4901B/GS4900B Preliminary Data Sheet
Assumption: Reference
XTAL is 27MHz+/-100ppm
+
t
t
+100ppm
+
t
+2ppm
-2ppm
27 MHz
-
t
-100ppm
-
t
Free Run
Genlock
Freeze
Time
No Input
Reference
Reference
Lost
Reference
Applied
NOTES:
1. t represents the temperature variability of the crystal
2. Diagram not to scale.
Figure 3-2: Output Accuracy and Modes of Operation
3.3 Output Timing Format Selection
At device power-up (described in Section 3.12 on page 88), the application layer
should immediately set the external VID_STD[5:0] and ASR_SEL[2:0] pins. The
VID_STD[5:0] pins are used to select a pre-programmed output video format. The
ASR_SEL[2:0] pins are only available on the GS4901B, and are used to select the
fundamental audio frequency or to turn off audio clock generation.
The output timing formats selectable by the user via the VID_STD[5:0] pins are
listed in Section 1.4 on page 20. Table 3-7 in Section 3.7.2 on page 53 lists the
audio sample rates available via the ASR_SEL[2:0] pins.
NOTE: The VID_STD[5:4] pins should be grounded by the application layer since
these pins are not required to select output video standards 1 to 10.
On power-up, the device will first check the status of the GENLOCK pin. If
GENLOCK is set LOW and a valid reference has been applied to the inputs, the
device will output the selected video standard while attempting to genlock.
However, if a reference signal has not been applied and GENLOCK=LOW, the
initial clock and timing outputs may be determined by the internal default settings
of the chip. If GENLOCK is set HIGH, the device will immediately enter Free Run
mode and will correctly output the selected video standard.
When operating in Free Run or Genlock mode, the GS4901B/GS4900B will
continuously monitor the settings of the VID_STD[5:0] and ASR_SEL[2:0] pins. If
the user wishes to change the format of the output clocks and timing signals, these
pins may be reconfigured at any time, although it is recommended that the device
be reset when changing output video standards.
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