GS4901B/GS4900B Preliminary Data Sheet
3. Detailed Description
3.1 Functional Overview
The GS4901B/GS4900B is a highly flexible, digitally controlled clock synthesis
circuit and timing generator with genlock capability.
The device has two main modes of operation: Genlock mode and Free Run mode.
In Genlock mode, the video clock and timing outputs, will be frequency and phase
locked to the detected reference input signal. In Free Run mode, the occurrence of
all frequencies is based on a 27MHz external crystal reference.
The GS4901B/GS4900B will recognize input reference signals conforming to 36
different video standards. It supports cross-locking, allowing the output to be
genlocked to an incoming reference that is different from the output video standard
selected.
When the device is in Genlock mode and the input reference is removed, the
GS4901B/GS4900B will enter Freeze mode. In this mode, the output clock and
timing signals will maintain their previously genlocked phase and frequency to
within +/- 2ppm.
The user may select to output one of 4 different video sample clock rates. The
chosen clock frequency may be further internally divided, and is available on two
video clock outputs and one LVDS video clock output pair. The video clocks may
also be individually phase delayed with respect to the timing outputs for clock skew
control.
Eight user-selectable timing outputs are provided that can automatically produce
the following timing signals for 9 different video formats: HSync, Hblanking, VSync,
Vblanking, F sync, F digital, AFS (GS4901B only), DE, and 10FID.
In addition, the GS4901B provides three audio sample clock outputs that can
produce audio clocks up to 512fs with fs ranging from 9.7kHz to 96kHz. Audio to
video phasing is accomplished by either an external 10FID input reference, a
10FID signal specified via internal registers, or a user-programmed audio frame
sequence.
3.2 Modes of Operation
The GS4901B/GS4900B will operate in either Genlock mode or Free Run mode
depending on the setting of the GENLOCK pin. These two modes are described in
Section 3.2.1 on page 35 and Section 3.2.2 on page 38 respectively.
If desired, the external GENLOCK pin may be ignored by setting bit 5 of the
Genlock_Control register (address 16h) so that genlock can instead be controlled
via the host interface (see Section 3.10.3 on page 66). Although the external
GENLOCK pin will be ignored in this case, it should not be left floating.
37703 - 0 April 2006
34 of 95
GENNUM [ GENNUM CORPORATION ]
