GS1560A/GS1561 Data Sheet
3.10.1 FIFO Load Pulse
To aid in the application-specific implementation of auto-phasing and line
synchronization functions, the GS1560A/GS1561 will generate a FIFO load pulse
to reset line-based FIFO storage.
The FIFO_LD output pin will normally be HIGH but will go LOW for one PCLK
period, thereby generating a FIFO write reset signal.
The FIFO load pulse will be generated such that it is co-timed to the SAV XYZ code
word presented to the output data bus. This ensures that the next PCLK cycle will
correspond to the first active sample of the video line.
Figure 3-5 shows the timing relationship between the FIFO_LD signal and the
output video data.
PCLK
LUMA DATA OUT
XYZ
(SAV)
3FF
3FF
000
000
000
000
XYZ
(SAV)
CHROMA DATA OUT
FIFO_LD
FIFO LOAD PULSE - HD 20BIT OUTPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
XYZ
(SAV)
XYZ
(SAV)
3FF
000
000
000
3FF
000
FIFO_LD
FIFO LOAD PULSE - HD 10BIT OUTPUT MODE
PCLK
3FF
000
000
CHROMA DATA OUT
XYZ
(SAV)
LUMA DATA OUT
FIFO_LD
FIFO LOAD PULSE - SD 20BIT OUTPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
XYZ
(SAV)
000
000
3FF
FIFO_LD
FIFO LOAD PULSE - SD 10BIT OUTPUT MODE
Figure 3-5: FIFO_LD Pulse Timing
27360 - 8 September 2005
47 of 80
GENNUM [ GENNUM CORPORATION ]
