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GS1561-CFE3 参数 Datasheet PDF下载

GS1561-CFE3图片预览
型号: GS1561-CFE3
PDF下载: 下载PDF文件 查看货源
内容描述: GS1560A / GS1561 HD - LINX -R II双率解串器 [GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer]
分类和应用: 存储静态存储器
文件页数/大小: 80 页 / 1307 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS1560A/GS1561 Data Sheet  
3.7.4 HVF Timing Signal Generation  
The GS1560A/GS1561 extracts critical timing parameters from either the received  
TRS signals (FW_EN/DIS = LOW), or from the internal flywheel-timing generator  
(FW_EN/DIS = HIGH).  
Horizontal blanking period (H), vertical blanking period (V), and even / odd field (F)  
timing are all extracted and presented to the application layer via the H:V:F status  
output pins.  
The H signal timing is configurable via the H_CONFIG bit of the internal  
IOPROC_DISABLE register as either active line based blanking, or TRS based  
blanking, (see Error Correction and Insertion on page 61).  
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this  
mode, the H output is HIGH for the entire horizontal blanking period, including the  
EAV and SAV TRS words. This is the default H timing used by the device.  
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H  
output will be HIGH for the entire horizontal blanking period as indicated by the H  
bit in the received TRS ID words.  
The timing of these signals is shown in Figure 3-3.  
27360 - 8 September 2005  
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