GS1531 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
A10, A9,
B10, B9,
C10, C9,
D10, D9,
E10, E9
Name
DIN[19:10]
Timing
Synchronous
with PCLK
Type
Input
Description
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DIN19 is the MSB and DIN10 is the LSB.
HD 20-bit mode
SD/HD = LOW
20bit/10bit = HIGH
Luma data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
HD 10-bit mode
SD/HD = LOW
20bit/10bit = LOW
Multiplexed Luma and Chroma data input
in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
SD 20-bit mode
SD/HD = HIGH
20bit/10bit = HIGH
Luma data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data input in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
SD 10-bit mode
SD/HD = HIGH
20bit/10bit = LOW
Multiplexed Luma and Chroma data input
in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data input in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
B1
B2
B3
B4
B7
CP_CAP
CP_VDD
CP_GND
LB_CONT
DETECT_TRS
Analog
–
–
Analog
Non
Synchronous
Input
Power
Power
Input
Input
PLL lock time constant capacitor connection.
Power supply connection for the charge pump. Connect to +3.3V DC
analog.
Ground connection for the charge pump. Connect to analog GND.
Control voltage to set the loop bandwidth of the integrated reclocker.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the timing mode of the device.
When set HIGH, the device will lock the internal flywheel to the embedded
TRS timing signals in the parallel input data.
When set LOW, the device will lock the internal flywheel to the externally
supplied H, V, and F input signals.
30573 - 4
July 2005
7 of 49
GENNUM [ GENNUM CORPORATION ]
