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GS1531-CBE2 参数 Datasheet PDF下载

GS1531-CBE2图片预览
型号: GS1531-CBE2
PDF下载: 下载PDF文件 查看货源
内容描述: GS1531 HD- LINX -TM II多速率串行器 [GS1531 HD-LINX-TM II Multi-Rate Serializer]
分类和应用: 消费电路商用集成电路
文件页数/大小: 49 页 / 853 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS1531 Data Sheet  
Table 1-1: Pin Descriptions (Continued)  
Pin  
Name  
Timing  
Type  
Description  
Number  
H6  
SDOUT_TDO  
Synchronous  
with  
Output  
CONTROL SIGNAL OUTPUT  
Signal levels are LVCMOS/LVTTL compatible.  
SCLK_TCK  
Serial Data Output / Test Data Output  
Host Mode (JTAG/HOST = LOW)  
SDOUT_TDO operates as the host interface serial output, SDOUT, used  
to read status and configuration information from the internal registers of  
the device.  
JTAG Test Mode (JTAG/HOST = HIGH)  
SDOUT_TDO operates as the JTAG test data output, TDO.  
H8  
H
Synchronous  
with PCLK  
Input  
CONTROL SIGNAL INPUT  
Signal levels are LVCMOS/LVTTL compatible.  
Used to indicate the portion of the video line containing active video data  
when DETECT_TRS is set LOW. The device will set the H bit in all  
outgoing TRS signals for the entire period that the H input signal is HIGH  
(IOPROC_EN/DIS must also be HIGH).  
H signal timing is configurable via the H_CONFIG bit of the  
IOPROC_DISABLE register, accessible via the host interface.  
Active Line Blanking (H_CONFIG = 0h)  
The H signal should be set HIGH for the entire horizontal blanking period,  
including the EAV and SAV TRS words, and LOW otherwise. This is the  
default setting.  
TRS Based Blanking (H_CONFIG = 1h)  
The H signal should be set HIGH for the entire horizontal blanking period  
as indicated by the H bit in the received TRS ID words, and LOW  
otherwise.  
J5  
SDO_EN/DIS  
Non  
Input  
CONTROL SIGNAL INPUT  
Synchronous  
Signal levels are LVCMOS/LVTTL compatible.  
Used to enable or disable the serial digital output stage.  
When set LOW, the serial digital output signals SDO and SDO are  
disabled and become high impedance.  
When set HIGH, the serial digital output signals SDO and SDO are  
enabled.  
J6  
SDIN_TDI  
Synchronous  
with  
Input  
CONTROL SIGNAL INPUT  
Signal levels are LVCMOS/LVTTL compatible.  
SCLK_TCK  
Serial Data In / Test Data Input  
Host Mode (JTAG/HOST = LOW)  
SDIN_TDI operates as the host interface serial input, SDIN, used to write  
address and configuration information to the internal registers of the  
device.  
JTAG Test Mode (JTAG/HOST = HIGH)  
SDIN_TDI operates as the JTAG test data input, TDI.  
NOTE: If the host interface is not being used, tie this pin HIGH.  
30573 - 4 July 2005  
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