GL860A USB 2.0 UVC Camera Controller
1
Test mode, Endpoint 0 can response all packet.
3
BULK_RST
EP1 bulk mode initial reset
2-0 EPnEN
Endpoint 1, 2, 3 TX/RX enable. (n=3~1)
After device is configured, EPTX1EN, EPTX2EN,EP3TXEN, EPRX1EN,
EPRX2EN,EP3RXEN write 1 to decide Endpoint 1,2,3 IN or OUT. Before
endpoint is enabled, it won’t response to any USB transaction.
Offset 4Bh – EPCTL2 …….…………………………………………..………… Default value = 8’h00
--
--
EP3TGRST EP2TGRST EP1TGRST
W/O W/O W/O
--
--
EP3STL
R/W
EP2STL
R/W
EP1STL
R/W
7
RESERVED
6-4 EPnTGRST
RESERVED
2-0 EPnSTL
-
Endpoint toggle reset. (n=3~1)
3
-
Endpoint stall. (n=3~1)
Offset 4Ch – EPCTL3 …….…………………………………………..………… Default value = 8’h00
EP3TOG
R/O
EP2TOG
R/O
EP1TOG TX3FFPOP FF3RST RX0FFPSH TX0FFPOP FF0RST
R/O R/W R/W R/W R/W R/W
7-5 EPnTOG
Toggle indication of DATA packet. (n=3~1)
uC pop endpoint 3 TXFIFO enable.
4
3
2
1
0
TX3FFPOP
FF3RST
Reset endpoint 3 FIFO read/write pointer. Data in FIFO remain unchanged.
uC push endpoint 0 RXFIFO enable
RX0FFPSH
TX0FFPOP
FF0RST
uC pop endpoint 0 TXFIFO enable.
Reset endpoint 0 TXFIFO read/write pointer. Data in FIFO remain unchanged.
Offset 4Dh – EPCTL3 …….…………………………………………..………… Default value = 8’h00
RX0DIS RXSETUP RXOUT
RXSEQ EP0RXSTL EP0TXSTL TX0OE
R/W R/W R/W R/W/C
TX0SEQ
R/W
R/W
R/O
R/O
7
RX0DIS
Disable receiving capability on endpoint 0
Upon successfully receiving a data packet on endpoint 0, hardware will automatically
set this bit to ‘1’. At this time, no more OUT data on endpoint 0 can be accepted,
hardware will respond with NAK. Note, for SETUP transaction, hardware will
always accept and respond with ACK.
0
1
Endp0 FIFO is available for data receiving.
Endp0 FIFO is not available
6
5
4
RXSETUP
RXOUT
RXSEQ
Endpoint 0 received token is SETUP.
Endpoint 0 received token is OUT.
Endpoint 0 received data toggle.
0
1
The received data is DATA0
The received data is DATA1
3
EP0RXSTL
Endpoint 0 receiving stall.
Endpoint 0 will respond with a STALL to a valid OUT transaction. This bit will
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