GL860A USB 2.0 UVC Camera Controller
3
2
1
0
SEN_CLKCTL3 Operating clock of sensor interface is 7.5M
SEN_CLKCTL2 Operating clock of sensor interface is 15M
SEN_CLKCTL1 Operating clock of sensor interface is 30M
SEN_CLKCTL0 Operating clock of sensor interface is 60M
Offset 11h – CPURST ………………..……………………………..………… Default value = 8’h00
CPU2SEN_
RST
--
--
--
--
--
--
--
--
--
--
--
--
--
--
R/W
7-1 RESERVED
-
0
CPU2SEN_RST
0
1
Unreset
Reset SEN_TOP
4.2.2 USB Register Part
Offset 40h – DEVCTL1 …………………………………………..…………… Default value = 8’h04
CHIRP_DEN
R/W
HS_SUSPD
R/W/C
TSTPKEN TSTPKRST
R/W/C W/O
--
--
DISGLUSB DIS_SUS
R/W R/W
PWRDN
R/W/C
7
HS_SUSPD
High Speed Suspend
This bit can be set/cleared by uC. When chip is in high speed mode and suspends
event is detected, uC can set HS_SUS and PWRDN bits to enter suspend mode.
This bit will be cleared automatically when end of resume signaling (K to SE0)
is detected.
6
5
4
CHIRP_DEN Set this bit will enable HS-KJKJKJ chirp detection. After correct HS chirp
sequence is detected, CHIRP_DET bit in USBEVT1 will be set.
TSTPKEN
Enable Endpoint 1 data packet transmission without receiving IN token.
This bit is cleared by hardware when TSTPKTX interrupt is set.
TSTPKRST
Reset Read Pointer of TX FIFO0.
Note: Write pointer & FIFO data keep unchanged.
3
2
RESERVED
DISGLUSB
-
When this bit is set to ‘1’, D+ pin will be left floating so that no connect will be
detected on the host side.
1
0
DIS_SUS
Disable suspend detection
PWRDN
`
Power down mode
If USB suspend is detected, firmware can set PWRDN to put the controller into
power down mode. Power down mode stops oscillator and freezes at known
states, and no more command can be executed. Hardware will automatically
clear PWRDN upon hardware reset or interrupted event.
Offset 41h – UEVT1 ………………………………………………..…………… Default value = 8’h00
CHIRP_DET
R/W1C
SOF
URST
WAKEUP RESUME
R/W1C R/W1C
SUSPD
R/W1C
EP0TX
R/W1C
EP0RX
R/W1C
R/W1C
R/W1C
©2007 GenesysLogic, Inc. - All rights reserved.
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GENESYS [ GENESYS LOGIC ]
