GL852 USB 2.0 MTT HUB Controller
USB2.0 HOST/HUB
USPORToperating
in HS signaling
HS vs. HS:
Traffic channel is
routed to REPEATER
HS vs. FS/LS:
Traffic channel
is routed to TT
TT
TT
REPEATER
DSPORT operating
in FS/LS signaling
DSPORT operating
in HS signaling
Figure 5.2 - Operating in USB 2.0 scheme
5.12 DSPORT logic
DSPORT (downstream port) logic implements the control logic defined in section 11.5 of USB
specification Revision 2.0. It mainly manipulates the state machine, the connection/disconnection detection,
over current detection and power enable control, and the status LED control of the downstream port.
Besides, it also output the control signals to the DSPORT transceiver.
5.13 DSPORT Transceiver
DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical
characteristics defined in chapter 7 of USB specification Revision 2.0. In addition, each DSPORT
transceiver accurately controls its own squelch level to detect the detachment and attachment of devices.
5.2 Configuration and I/O Settings
5.2.1 RESET# Setting
GL852’s power on reset can either be triggered by external reset or internal power good reset circuit. The
external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V
voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested
value refers to schematics) GL852’s internal reset is designed to monitor silicon’s internal core power (3.3V)
and initiate reset when unstable power event occurs. The power on sequence will start after the power good
voltage has been met, and the reset will be released after approximately 2.7 nS after power good. GL852’s
reset circuit as depicted in the picture
©2000-2009 Genesys Logic Inc. - All rights reserved.
Page 20
GENESYS [ GENESYS LOGIC ]
