GL850G USB 2.0 Low-Power HUB Controller
CHAPTER 4 BLOCK DIAGRAM
12MHz
D+
D-
USPORT
PLL
RAM ROM
CPU
GPIO
FRTIMER
Transceiver
x40, x10
Control/Status
Register
USPORT
Logic
UTMI
SIE
REPEATER
TT (Transaction Translator)
REPEATER / TT Routing Logic
DSPORT1 Logic
DSPORT2 Logic
DSPORT3 Logic
DSPORT4 Logic
DSPORT
Transceiver
DSPORT
Transceiver
DSPORT
Transceiver
DSPORT
Transceiver
LED/
LED/
OVCUR/
LED/
OVCUR/
LED/
D+ D-
OVCUR/
D+ D-
D+ D-
D+ D-
OVCUR/
PWRENB
PWRENB
PWRENB
PWRENB
Figure 4.1 – GL850G Block Diagram (single TT)
©2000-2007 Genesys Logic Inc. - All rights reserved.
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