MB90560/565 Series
■ BLOCK DIAGRAM
X0, X1
RST
MD0 to MD2
Clock
control circuit
F2MC-16LX
CPU
Interrupt controller
8/16-bit
PPG timer
PPG0 to PPG5
IN0 to IN3
RAM
ROM
ch0 to ch5*
Input
capture
SIN0
SOT0
SCK0
ch0 to ch3
UART
ch0
SIN1
SOT1
SCK1
16-bit
freerun
timer
UART
ch1
FRCK
AVCC
AVR
8/10-bit
RTO0
RTO1
RTO2
RTO3
RTO4
RTO5
DTTI
AVSS
AN0 to AN7
A/D converter
Output
compare
ch0 to ch5
16-bit
reload timer
ch0
TO0
TIN0
Waveform generator circuit
16-bit
reload timer
ch1
TO1
TIN1
DTP/
external interrupts
INT0 to INT7
I/O ports (Ports 0, 1, 2, 3, 4, 5, and 6)
P00
P07
P10
P17
P20
P27
P30
P37
P40
P46
P50
P57
P60
P63
* : Channel numbers when used as 8-bit timers. Three channels (ch1, ch3, and ch5) are available when used
as 16-bit timers.
Note: The I/O ports share pins with the various peripheral functions (resources) .
See the Pin Assignment and Pin Description sections for details.
Note that, if a pin is used by a peripheral function (resource) , it may not be used as an I/O port.
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