MB90480/485 Series
(2) Block Diagram
ICCR
I2C enable
Clock dividing 1
EN
Peripheral clock
5
6
7
8
ICCR
CS4
CS3
Clock selection 1
Clock dividing 2
CS2
2
4
8
16 32 64 128 256
Sync
Shift clock generation
CS1
CS0
Clock selection 2
Change timing
of shift clock edge
IBSR
Bus busy
BB
Repeat start
Last Bit
RSC
LRB
TRX
FBT
AL
Start/stop condition detection
Transmission/
Reception
Error
First Byte
Arbitration lost detection
IBCR
SCL
SDA
BER
BEIE
Interrupt request
IRQ
INTE
INT
IBCR
End
Start
SCC
Master
MSS
ACK
Start/stop condition
detection
ACK enable
GC-ACK enable
GCAA
IDAR
IBSR
Slave
AAS
Slave address
comparison
Global call
GCA
IADR
58
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