MB90480/485 Series
7. DTP/External Interrupt
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16LX CPU to activate the extended intelligent µDMAC or interrupt processing.
(1) Detailed Register Descriptions
Interrupt/DTP Enable Register (ENIR : Enable Interrupt Request Register)
ENIR
Address : 00000CH
Initial value
00000000B
7
6
5
4
3
2
1
0
EN7
R/W
EN6
R/W
EN5
R/W
EN4
R/W
EN3
R/W
EN2
R/W
EN1
R/W
EN0
R/W
Interrupt/DTP Source Register (EIRR : External Interrupt Request Register)
EIRR
Initial value
15
14
13
12
11
10
9
8
Address : 00000DH
XXXXXXXXB
ER7
R/W
ER6
R/W
ER5
R/W
ER4
R/W
ER3
R/W
ER2
R/W
ER1
R/W
ER0
R/W
Interrupt Level Setting Register (ELVR : External Level Register)
Initial value
00000000B
7
6
5
4
3
2
1
0
Address : 00000EH
LB3
R/W
LA3
R/W
LB2
R/W
LA2
R/W
LB1
R/W
LA1
R/W
LB0
R/W
LA0
R/W
Initial value
00000000B
15
14
13
12
11
10
9
8
Address : 00000FH
LB7
R/W
LA7
R/W
LB6
R/W
LA6
R/W
LB5
R/W
LA5
R/W
LB4
R/W
LA4
R/W
(2) Block Diagram
F2MC-16 bus
4
Interrupt/DTP enable register
4
4
8
4
Edge detection
circuit
Source F/F
Gate
Request input
Interrupt/DTP source register
Interrupt level setting register
49
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