MB90480/485 Series
• 8-bit PPG ch.1/3/5 Block Diagram
PPG1/3/5 output
Peripheral clock × 16
enable
PPG1/3/5
UART0
Peripheral clock × 8
Peripheral clock × 4
Peripheral clock × 2
Peripheral clock
PPG1/3/5
output latch
PEN1
S
R
PCNT
(down counter)
Q
IRQ
Count clock
select
“L”/“H” selector
Timebase counter
output main clock × 512
PIE1
PUF1
“L”/“H” select
PRLL
PRLL
PRLBH
PPGC1 (operation mode control)
“L” data bus
“H” data bus
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