MB90480/485 Series
(2) Block Diagram
•8-bit PPG ch.0/2/4 block Diagram
PPG0/2/4
output enable
Peripheral clock × 16
Peripheral clock × 8
Peripheral clock × 4
Peripheral clock × 2
Peripheral clock
PPG0/2/4
A/D converter
PPG0/2/4
output latch
PEN0
S
PCNT
(down counter)
Q
R
IRQ
Count clock
select
ch.1/3/5 borrow
“L”/“H” selector
Timebase counter
output main clock
× 512
PIE0
PUF0
“L”/“H” select
PRLL
PRLL
PRLBH
PPGC0 (operation mode control)
“L” data bus
“H” data bus
44