MB90480/485 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
µDMAC
channel
number
Interrupt vector
Interrupt control register
Clear of
EI2OS
Interrupt source
Number Address
Number
Address
Reset
×
×
×
⎯
⎯
⎯
0
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
⎯
⎯
⎯
⎯
⎯
⎯
INT9 instruction
Exception
INT0 (IRQ0)
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
INT1 (IRQ1)
×
INT2 (IRQ2)
×
INT3 (IRQ3)
×
INT4 (IRQ4)
×
INT5 (IRQ5)
×
INT6 (IRQ6)
×
INT7 (IRQ7)
×
PWC1 (MB90485 series only)
PWC2 (MB90485 series only)
PWC0 (MB90485 series only)
PPG0/PPG1 counter borrow
PPG2/PPG3 counter borrow
PPG4/PPG5 counter borrow
×
×
1
×
×
×
×
×
×
8/16-bit up/down counter/
timer (ch.0, ch.1) compare/
underflow/overflow/up/down
inversion
×
#25
FFFF98H
ICR07
0000B7H
Input capture (ch.0) load
5
6
#26
#27
#28
#29
#30
#31
#32
#33
#34
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
Input capture (ch.1) load
ICR08
ICR09
ICR10
ICR11
0000B8H
0000B9H
0000BAH
0000BBH
Output compare (ch.0) match
Output compare (ch.1) match
Output compare (ch.2) match
Output compare (ch.3) match
Output compare (ch.4) match
Output compare (ch.5) match
UART sending completed
8
9
10
×
×
×
11
16-bit free run timer overflow,
16-bit reload timer underflow*2
12
#35
FFFF70H
ICR12
ICR13
0000BCH
UART receiving completed
SIO1 (ch.0)
7
#36
#37
#38
FFFF6CH
FFFF68H
FFFF64H
13
14
0000BDH
SIO2 (ch.1)
(Continued)
31