MB95120MB Series
(Continued)
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Value*2
Sym- Pin
bol name
Parameter
Condition
Unit
Remarks
Min
Max
Undetected when 1
ns tMCLK is used at
reception
Stop condition
detection
SCL0
tSU;STO
2 tMCLK − 20
⎯
SDA0
Undetected when 1
ns tMCLK is used at
reception
Restart condition
detection condition
SCL0
tSU;STA
2 tMCLK − 20
⎯
SDA0
SCL0
tBUF
2 tMCLK − 20
2 tMCLK − 20
tLOW − 3 tMCLK − 20
0
Bus free time
⎯
⎯
⎯
⎯
⎯
ns At reception
SDA0
SCL0
tHD;DAT
At slave transmission
mode
Data hold time
Data setup time
Data hold time
Data setup time
ns
SDA0
R = 1.7 kΩ,
C = 50 pF*1
SCL0
tSU;DAT
At slave transmission
mode
ns
SDA0
SCL0
tHD;DAT
ns At reception
ns At reception
SDA0
SCL0
tSU;DAT
tMCLK − 20
SDA0
Oscillation
stabilization
wait time +
2 tMCLK − 20
SDA↓→SCL↑
(at wakeup function)
tWAKE- SCL0
⎯
ns
UP
SDA0
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• m is CS4 bit and CS3 bit (bit 4 and bit 3) of I2C clock control register (ICCR) .
• n is CS2 bit to CS0 bit (bit 2 to bit 0) of I2C clock control register (ICCR) .
• Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
• Fast-mode :
: 0.9 MHz < tMCLK ≤ 10 MHz
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
(m, n) = (1, 22) , (5, 4)
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 4 MHz
: 3.3 MHz < tMCLK ≤ 8 MHz
: 3.3 MHz < tMCLK ≤ 10 MHz
60
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