MB95120MB Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
Max
⎯
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK, SOT
−95
+95
⎯
Internal clock
SCK, SIN operating output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK ↑ → valid SIN hold time
SOT → SCK ↑ delay time
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSOVHI
tIVSHI
tSLOVI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tSHIXI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
56