October 1996
Revision 1.0
EDC8UV724(2/4)-(60/70)(J/T)G-S
DC CHARACTERISTICS
(V
CC
= 3.3V±0.3V, V
SS
= 0V, T
A
= 0 to +70
°C)
60
Parameter
Symbol
Test Condition
Refresh
Min.
Operating Current
I
CC11
RAS*, CAS* cycling; t
RC
= min..
LVTTL Interface
RAS*, CAS*
≥
V
IH
D
out
= High-Z
CMOS Interface
RAS*, CAS*
≥
V
cc
- 0.2V
D
out
= High-Z
CAS*
≥
V
IH
; RAS*, Address
cycling @ t
RC
= min
RAS*, CAS* cycling @
t
RC
= min.
RAS*
≤
V
IL
CAS*, Address
cycling @ t
PC
= min
0V
≤
V
in
≤
V
CC
+0.3V
0V
≤
V
out
≤
V
CC
D
out
= Disable
High I
out
= -2mA
Low I
out
= 2 mA
2KR
4KR
2KR
4KR
2KR
4KR
2KR
4KR
-
-
-
Max.
2016
1476
72
Min.
-
-
-
Max.
1746
mA
1296
72
mA
1, 2
70
Unit
Note
Standby current
I
CC2
-
-
-
-
-
-
-
-360
-20
2.4
-
36
2016
1476
2016
1476
1836
1656
360
20
-
0.4
-
-
-
-
-
-
-
-360
-20
2.4
-
36
1746
mA
2
mA
RAS* -only Refresh
Current
CAS*-before-RAS*
Refresh Current
Hyper Page Mode
Currentt
Input Leakage Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
Notes:
1.
2.
3.
I
CC3
1296
1746
mA
1296
1656
1476
360
20
-
0.4
mA
mA
1, 2
1, 3
1, 2
I
CC4
I
CC5
I
LI
I
LO
V
OH
V
OL
µ
A
µ
A
V
V
Values depend on output load condition when the device is selected. Maximum Values are specified at the output open condition.
Address can be changed once or less while RAS* = V
IL
.
Address can be changed once or less while CAS* = V
IH
.
CAPACITANCE
(TA =+25°C, V
CC
= 3.3V±0.3V)
Parameter
Input Capacitance (Address)
Input Capacitance (RAS0*~ RAS3*)
Input Capacitance (OE0*,OE2*,WE0*,WE2*)
Input Capacitance (CAS0*~CAS7*)
Input/Output Capacitance (DQ0~DQ63, C0~C7)
Notes:
1.
2.
Symbol
C
I1
C
I2
C
I3
C
I4
C
I/O
Max.
185
68
131
47
20
Unit
pF
pF
pF
pF
pF
Note
1
1
1
1
1, 2
Capacitance is measured with Boonton Meter or effective capacitance method.
CAS* = V
IH
to disable D
out
.
4
Fujitsu Microelectronics, Inc.
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
