October 1996
Revision 1.0
EDC8UV724(2/4)-(60/70)(J/T)G-S
Functional Diagram
CAS7*
CAS6*
CAS5*
CAS4*
CAS3*
CAS2*
CAS1*
CAS0*
OE0*
WE0*
RAS0*
4M x 8
Block
4MX12
Block
4M x 8
Block
OE2*
4M x 8
WE2*
Block
RAS2*
4M x 8
Block
4M x12
Block
4M x 8
Block
4M x 8
Block
4M x 8
Block
RAS1*
4MX12
Block
4M x 8
Block
C0~C3
4M x 8
Block
RAS3*
4M x 8
Block
4M x12
Block
4M x 8
Block
4M x 8
Block
C4~C7
D16~D23
D24~D31
D32~D39
D40~D47
D48~D55
D56~D63
D0~D7
D8~D15
DQ0~DQ63, C0~CB7
SA0
SA1
SA2
SCL
SDA
Serial
EEPROM
Device
V
CC
V
SS
Decoupling capacitors
to all devices
(All specifications of the device are subject to change without notice.)
Notes:
1.
2.
3.
4.
“*” signifies active low signal.
Addresses A0 ~ A10/A11 are connected to all devices.
(A11 is NC for 2K refresh module)
Each 4Mx8 block contains two 4Mx4 devices, and each 4Mx12 block contains three 4Mx4 devices.
2
Fujitsu Microelectronics, Inc.
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
