MBM29LV800TE/BE60/70/90
Write Operation Status
Hardware Sequence Flags
Status
DQ7
DQ7
0
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
1
Toggle
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
0
Toggle
Data
1*2
In Progress
Erase
Erase Suspend Read
Suspended
Data
DQ7
Data
Data Data
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle*1
0
0
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7
0
Toggle
Toggle
1
1
0
1
1
N/A
Exceeded
Erase
Time Limits
Erase Suspend Program
Suspended
DQ7
Toggle
1
0
N/A
(Non-Erase Suspended Sector)
Mode
*1 : Performing successive read operations from any address will cause DQ6 to toggle.
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
Notes : • DQ1 and DQ0 are reserved pins for future use.
• DQ4 is Fujitsu internal use only.
DQ7
Data Polling
The MBM29LV800TE/BE devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read devices
will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm,
an attempt to read device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an
attempt to read device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm
an attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “Data
Polling Algorithm” in “■ FLOW CHART”.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected
sectors. Otherwise, the status may be invalid. Once the Embedded Algorithm operation is close to completion,
MBM29LV800TE/BE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low.
This means that devices are driving status information on DQ7 at one instant of time and then that byte’s valid
data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status
or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data
outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on the successive read
attempts.
TheDataPollingfeatureisactiveonlyduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm
or sector erase time-out.
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the
Data Polling timing specifications and diagrams.
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FUJITSU [ FUJITSU ]
