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VNC2-48Q1B-TRAY 参数 Datasheet PDF下载

VNC2-48Q1B-TRAY图片预览
型号: VNC2-48Q1B-TRAY
PDF下载: 下载PDF文件 查看货源
内容描述: [Vinculum-II Embedded Dual USB Host Controller IC]
分类和应用:
文件页数/大小: 88 页 / 2234 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Datasheet  
Vinculum-II Embedded Dual USB Host Controller IC  
Version 1.7  
Document No.: FT_000138 Clearance No.: FTDI#143  
The command and status formats for this mode can be seen in Figure 6.15 below with a description of  
each field in Table 6.7.  
Command:  
Data:  
Start  
D7  
R/W  
D6  
Addr  
D5  
D4  
D3  
D2  
D1  
D0  
Status:  
Status  
Figure 6.15 VNC1L Compatible SPI Command and Status Structure  
Field  
Description  
Start  
Driven to ‘1’.  
If set to 1’, the SPI Master wishes to read from the slave. If set to ‘0’, the SPI Master wishes to  
write to the slave.  
R/W  
If set to 1, a read operation will return the status byte in the data phase. A write will have no  
effect.  
Addr  
If set to ‘0’, a read or a write will operate on the data register.  
D7:D0  
Status  
Data.  
When ‘0’ this means a read or write was successful. When ‘1’ it means a read contains old data,  
or a write did not work and needs retried.  
Table 6.7 SPI Command and Status Fields  
6.3.6.1 SPI Setup Bit Encoding  
The VNC1L compatible SPI interface differs from most other implementations in that it uses a 12 clock  
sequence to transfer a single byte of data. In addition to a ‘Start’ state, the SPI master must send two  
setup bits which indicate data direction and target address. The encoding of the setup bits is shown in  
Table 6.8. A single data byte is transmitted in each SPI transaction, with the most significant bit  
transmitted first.  
After each transaction VNC2 returns a single status bit. This indicates if a Data Write was successful or a  
Data Read was valid.  
Direction  
(R/W)  
Target  
Address  
Operation  
Meaning  
1
1
0
0
0
1
0
1
Data Read  
Status Read  
Data Write  
N/A  
Retrieve byte from Transmit Buffer  
Read SPI Interface Status  
Add byte to Receive Buffer  
N/A  
Table 6.8 SPI Setup Bit Encoding  
49  
Copyright © Future Technology Devices International Limited  
 
 
 
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