2.�½�½ �½PI Inter�½a�½e �½igna�½�½ �½es�½riptions and Timing �½iagrams
2.�½�½ �½PI Inter�½a�½e �½igna�½�½ �½es�½riptions and Timing �½iagrams
Page
Table 8 - Data and Control Bus Signal Mode Options - SPI Interface
Pin No.
14
16
17
18
Name
SCLK
SDI
SDO
CS
Type
Input
Input
Output
Input
Description
SPI Clock input, 12MHz maximum.
SPI Serial Data Input
SPI Serial Data Output
SPI Chip Select Input
Figure 5 - SPI Slave Data Read Cycle
R/W ADD D7
SPICLK
SPI CS
SPI Data In
1
SPI Data Out
Start
D6
D5
D4
D3
D2
D1
D0
1
0
From Start - SPI CS must be held high for the entire read cycle, and must be taken low for at least one clock period
after the read is completed. The first bit on SPI Data In is the R/W bit - inputting a ‘1’ here allows data to be read from
the chip. The next bit is the address bit, ADD, which is used to indicate whether the data register (‘0’) or the status
register (‘1’) is read from. During the SPI read cycle a byte of data will start being output on SPI Data Out on the next
clock cycle after the address bit, MSB first. After the data has been clocked out of the chip, the status of SPI Data
Out should be checked to see if the data read is new data. A ‘0’ level here on SPI Data Out means that the data read
is new data. A ‘1’ indicates that the data read is old data, and the read cycle should be repeated to get new data.
Remember that CS must be held low for at least one clock period before being taken high again to continue with the
next read or write cycle.
Figure 6 - SPI Slave Data Write Cycle
R/W ADD D7
SPICLK
SPI CS
SPI Data In
1
SPI Data Out
Start
D6
D5
D4
D3
D2
D1
D0
0
0
From Start - SPI CS must be held high for the entire write cycle, and must be taken low for at least one clock period
after the write is completed. The first bit on SPI Data In is the R/W bit - inputting a ‘0’ here allows data to be written
to the chip. The next bit is the address bit, ADD, which is used to indicate whether the data register (‘0’) or the status
VDIP2 Vinculum VNC1L Prototyping Module
Datasheet Version 0.91
© Future Technology Devices Intl Ltd. 2006-2007
Status
Status
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