VDIP2 参数 Datasheet PDF下载

2.�½�½ Para�½�½�½�½e�½�½ �½I�½O Inter�½a�½e �½igna�½�½ �½es�½riptions and Timing �½iagrams

2.�½�½ Para�½�½�½�½e�½�½ �½I�½O Inter�½a�½e �½igna�½�½ �½es�½riptions and Timing �½iagrams

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Table 5 - Data and Control Bus Signal Mode Options - Parallel FIFO Interface

Pin No.

14

16

17

18

19

20

21

22

23

24

25

27

Name

D0

D1

D2

D3

D4

D5

D6

D7

RXF#

TXE#

RD#

WR

Type

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

OUTPUT

OUTPUT

INPUT

INPUT

Description

FIFO Data Bus Bit 0

FIFO Data Bus Bit 1

FIFO Data Bus Bit 2

FIFO Data Bus Bit 3

FIFO Data Bus Bit 4

FIFO Data Bus Bit 5

FIFO Data Bus Bit 6

FIFO Data Bus Bit 7

When high, do not read data from the FIFO. When low, there is data available in the FIFO which can

be read by strobing RD# low, then high again.

When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing

WR high, then low.

Enables the current FIFO data byte on D0...D7 when low. Fetched the next FIFO data byte (if avail-

able) from the receive FIFO buffer when RD# goes from high to low.

Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR goes from high to low.

Figure 3 - FIFO Read Cycle

T6

RXF#

T5

RD#

T3

T1

T2

T4

Valid Data

D[7...0]

Table 6 - FIFO Read Cycle Timings

Time

T1

T2

T3

T4

T5

T6

Description

RD Active Pulse Width

RD to RD Pre-Charge Time

RD Active to Valid Data*

Valid Data Hold Time from RD Inactive*

RD Inactive to RXF#

RXF Inactive After RD Cycle

Min

50

50 + T6

20

0

0

80

Max

-

-

50

-

25

-

Unit

ns

ns

ns

ns

ns

ns

* Load = 30pF

VDIP2 Vinculum VNC1L Prototyping Module

Datasheet Version 0.91

© Future Technology Devices Intl Ltd. 2006-2007