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register (‘1’) is written to. During the SPI write cycle a byte of data can be input to SPI Data In on the next clock cycle
afterꢀtheꢀaddressꢀbit,ꢀMSBꢀfirst.ꢀAfterꢀtheꢀdataꢀhasꢀbeenꢀclockedꢀinꢀtoꢀtheꢀchip,ꢀtheꢀstatusꢀofꢀSPIꢀDataꢀOutꢀshouldꢀbeꢀ
checked to see if the data read was accepted. A ‘0’ level on SPI Data Out means that the data write was accepted. A
‘1’ indicates that the internal buffer is full, and the write should be repeated. Remember that CS must be held low for at
least one clock period before being taken high again to continue with the next read or write cycle.
Figure 7 - SPI Slave Data Timing Diagrams
T1
SPICLK
T2
T3
SPICS /
SPI DATA IN
T6
T4
T5
SPI DATA OUT
T7
Table 9 - SPI Slave Data Timing
Time
T1
Description
SPICLK Period
SPICLK High
Min
83
20
20
10
10
2
Typical Max
Unit
ns
-
-
-
-
-
-
-
-
T2
-
ns
T3
SPICLK Low
-
ns
T4
Input Setup Time
Input Hold Time
Output Hold Time
Output Valid Time
-
ns
T5
-
ns
T6
-
ns
T7
-
20
ns
Table 10 - Status Register (ADD = ‘1’)
Bit
0
Description
RXF#
1
TXE#
2
-
3
-
4
RXFꢀIRQEn
5
TXEꢀIRQEn
6
-
-
7
VDIP2 Vinculum VNC1L Prototyping Module
Datasheet Version 0.91
© Future Technology Devices Intl Ltd. 2006-2007
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
