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Document Reference No.: FT_000198
MORPH-IC-II Datasheet
Version 1.02
Clearance No.: FTDI#
164
3.5.4 Pin-Map Configuration
The Cyclone-II FPGA of the Morph-IC-II can be configured from an *.RBF file. These *.RBF files can be
generated using the free software package called Quartus II. An *.RBF file generated by Quartus II
contains the *.RTL code which synthesises the circuit, the signals of each pin (which are defined in the
top level entity of the *.RTL) and the settings of each pin (which includes current draw and logic level
standards). The pin map editor included in Quartus-II is used to specify the signal assignments and the
setting of each pin.
Along with making pin assignment to each port of the top-level entity, the voltage and current can be
defined for each port. However there are restrictions, every signal in an I/O Bank needs to operate at the
same
logic voltage level
and the I/O Bank needs to be powered with the same voltage as the
logic
voltage level
of the signals. Morph-IC-II‟s I/O Banks 1 to 3 are connected directly to the FT2232H chip
and all these signals are fixed to 3.3V-TTL/CMOS. I/O Bank 4 is the only bank that can have signals
operating at voltages other than 3.3V-TTL/CMOS. Again all signals need to be at the same
logic voltage
level,
to supply power with a voltage other than 3.3V, remove V_BANK4 jumper and apply DC power
regulated to the same voltage level as the
logic voltage level
of I/O Bank4 to (at least one of) the header
nodes labelled V_BANK4. More information and an example for pin-map editing are given in the
application note: AN_141_MorphIO-II and MorphLd Utilities for Morph-IC-II
Copyright © 2010 Future Technology Devices International Limited
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