Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.7
Document No.: FT_000138 Clearance No.: FTDI#143
Figure 2.1 Simplified VNC2 Block Diagram..............................................................................................3
Figure 3.1 32 Pin LQFP – Top Down View...............................................................................................7
Figure 3.2 32 Pin QFN – Top Down View................................................................................................8
Figure 3.3 48 Pin LQFP – Top Down View...............................................................................................9
Figure 3.4 48 Pin QFN – Top Down View...............................................................................................10
Figure 3.5 64 Pin LQFP – Top Down View.............................................................................................11
Figure 3.6 64 Pin QFN – Top Down View...............................................................................................12
Figure 3.7 Schematic Symbol 32 Pin.....................................................................................................13
Figure 3.8 Schematic Symbol 48 Pin.....................................................................................................14
Figure 3.9 Schematic Symbol 64 Pin.....................................................................................................15
Figure 5.1 IOBUS to Group Relationship-64 Pin.....................................................................................25
Figure 5.2 IOBUS to UART, SPI slave0 and SPI master example............................................................26
Figure 5.3 IOBUS to UART, SPI slave0 and SPI master second example ................................................27
Figure 5.4 IOBUS to UART, SPI slave0 and SPI master third example....................................................28
Figure 5.5 VNC2 Toolchain App Wizard showing IOMux Configuration....................................................30
Figure 5.6 UART Example 64 pin...........................................................................................................35
Figure 6.1 UART Receive Waveform......................................................................................................36
Figure 6.2 UART Transmit Waveform....................................................................................................36
Figure 6.3 - SPI CPOL CPHA Function....................................................................................................41
Figure 6.4 SPI Slave block diagram ......................................................................................................41
Figure 6.5 Full Duplex Data Master Write..............................................................................................43
Figure 6.6 Full Duplex Data Master Read ..............................................................................................43
Figure 6.7 SPI Command and Status Structure.....................................................................................44
Figure 6.8 Half Duplex Data Master Write .............................................................................................45
Figure 6.9 Half Duplex Data Master Read..............................................................................................45
Figure 6.10 Half Duplex 3-pin Data Master Write ..................................................................................46
Figure 6.11 Half Duplex 3-pin Data Master Read...................................................................................46
Figure 6.12 Unmanaged Mode Transfer Diagram...................................................................................47
Figure 6.13 VNC1L Mode Data Write.....................................................................................................48
Figure 6.14 VNC1L Mode Data Read......................................................................................................48
Figure 6.15 VNC1L Compatible SPI Command and Status Structure ......................................................49
Figure 6.16 SPI Slave Mode Timing.......................................................................................................50
Figure 6.17 SPI Master Data Read (VNC2 Slave Mode)..........................................................................51
Figure 6.18 SPI Slave Mode Data Write.................................................................................................52
Figure 6.19 SPI Slave Mode Status Read ..............................................................................................52
Figure 6.20 SPI Master block diagram...................................................................................................53
Figure 6.21 Typical SPI Master Timing ..................................................................................................55
Figure 6.22 Asynchronous FIFO mode Read / Write Cycle .....................................................................60
Figure 6.23 Synchronous FIFO mode Read / Write Cycle .......................................................................62
Figure 6.24 PWM – Timing Diagram......................................................................................................64
Figure 6.25 GPIO Port Groups...............................................................................................................64
Figure 7.1 USB Modes ..........................................................................................................................65
Figure 10.1 VNC2 Schematic (MCU – UART Interface)...........................................................................72
Figure 11.1 Package Markings ..............................................................................................................73
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