Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.7
Document No.: FT_000138 Clearance No.: FTDI#143
Status Bit
Meaning
Data in current transaction is valid data.
Byte removed fromTransmit Buffer.
0
New Data
Old Data
This same data hasbeen read in a previous readcycle.
Repeat the readcycle until New Data is received.
1
Table 6.10 SPI Master Data Read Status Bit
Figure 6.17 SPI Master Data Read (VNC2 Slave Mode)
The status bit is only valid until the next rising edge of SCLK after the last data bit.
During the Data Read operation the SS signal must not be de-asserted.
The transfer completes after 12 clock cycles and the next transfer can begin when MOSI and SS are high
during the rising edge of SCLK.
6.3.6.3 SPI Master Data Write Transaction in VNC1L legacy mode
During an SPI master Data Write operation the Start and Setup sequence is sent by the SPI master to
VNC2, see Figure 6.18. This is followed by the SPI master transmitting each bit of the data to be written
to VNC2. The VNC2 then responds with a status bit on MISO on the rising edge of the next clock cycle.
The SPI master must read the status bit at the end of each write transaction to determine if the data was
written successfully to VNC2 Receive Buffer. The Data Write status bit is defined in Table 6.11.The
status bit is only valid until the next rising edge of SCLK after the last data bit.
If the status bit indicates Accept then the byte transmitted has been added to VNC2 Receive Buffer. If it
shows Reject then the Receive Buffer is full and the byte of data transmitted in the current transaction
should be re-transmitted by the SPI master to VNC2.
Any application should poll VNC2 Receive Buffer by retrying the Data Write operation until the data is
accepted.
Status Bit
Meaning
0
1
Accept
Reject
Data from the current transactionwas acceptedand addedto the Receive Buffer
Write data was not accepted. Retry the same write cycle.
Table 6.11 SPI Master Data Write Status Bit
51
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