Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.7
Document No.: FT_000138 Clearance No.: FTDI#143
6.2 Serial Peripheral Interface – SPI Modes
The Serial Peripheral Interface Bus is an industry standard communications interface. Devices
communicate in Master / Slave mode, with the Master initiating the data transfer.
VNC2 has one master module and two slave modules. Each SPI slave module has four signals – clock,
slave select, MOSI (master out – slave in) and MISO (master in – slave out). The SPI Master has the
same four signals as the slave modules but with one additional signal because it requires a slave select
for the second slave module. Table 6.2 lists how the signals are named in each module.
The SPI Master clock can operate up to one half of the CPU system clock depending on what power mode
the device is set to:
Normal power mode 48Mhz would set the SPI maximum clock to 24Mhz
Low power mode 24Mhz would setthe SPI maximum clock to 12Mhz
Lowest power mode 12Mhz would set the SPI maximum clock to 6hMz
Module
Signal Name
Type
Description
spi_s0_clk
spi_s0_ss#
spi_s0_mosi
spi_s0_miso
spi_s1_clk
Input
Input
Clock input – slave 0
Active low chip select input – slave 0
Master out serial in – slave 0
Master in slave out – slave 0
Clock input – slave 1
SPI Slave
0
Input
Output
Input
spi_s1_ss#
spi_s1_mosi
spi_s1_miso
spi_m_clk
Input
Active low chip select input – slave 1
Master out slave in – slave 1
Master in slave out – slave 1
Clock output – master
SPI Slave
1
Input
Output
Output
Output
Input
spi_m_mosi
spi_m_miso
spi_m_ss_0#
spi_m_ss_1#
Master out slave in - master
SPI Master
Master in slave out - master
Output
Output
Active low slave select 0 from masterto slave 0
Active low slave select 1 from masterto slave 1
Table 6.2 SPI Signal Names
The SPI slave protocol by default does not support any form of handshaking. FTDI have added extra
modes to support handshaking, faster throughput of data and reduced pin count. There are 5 modes
(Table 15) of operation in the VNC2 SPI Slave.
Full Duplex – Section 0
Half Duplex, 4 pin - Section 6.3.3
Half Duplex, 3 pin - Section 6.3.4
Unmanaged - Section 6.3.5
VNC1L legacy mode – Section 6.3.6
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